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PCIE接口  VPX信号处理卡

The VPX-D16A4-PCIE is a rugged high performance DSP/FPGA card in the compact VITA 65, 3U OpenVPX form factor. It is ideal for applications such as EW, SW radio, imaging or radar in harsh field deployment environments.

The card features 4x ARM A15 cores, 16x C66x+ DSP cores and various accelerators across two TI Keystone SoCs, each with its own large DDR3 memory bank and a 10Gbaud 2x PCIe link to the VPX backplane. They are closely coupled with the HyperLink bus. The main DSP has SRIO and CPRI links to a Xilinx Kintex-7 K325T FPGA, which has its own backplane MGT, LDVS, GPIO, serial ports and a flexible PLL, enabling I/O such as RF or ADC/DAC interfaces. All devices also have Gigabit Ethernet connectivity.

A full Linux BSP and example software support is provided to accelerate customer development, based on TI’s Linux and Multicore Software Development Kit and the Xilinx Vivado FPGA development suite. In addition, field proven LTE software from MIMOon is available integrated with the card.

Key Features

Form Factor:  

  • 3U OpenVPX card conforming to  AV65-2010, 1” pitch and a payload  profile of MOD3-PAY-2F2U-16.2.3-8

  • Rugged conduction or air cooled

  • Universal keying (unkeyed)

DSP0: Texas Instruments TCI6636/38 o66AK2H12/14 KeystoneII DSP/ARM SoC

  • 4 x 1.4 GHz ARM A15 cores

  • 8 x 1.2 GHz C66x DSP cores Wireless accelerators (TCI parts only)

  •  2 Gbytes x64 DDR3-1600 SDRAM

  •  256 Mbytes x16 boot FLASH

  • GigE to FPGA0, DSP1 and backplane

  •  HyperLink to DSP1 at up to 50 Gbaud

  •  2x 5Gbaud Gen2 PCIe to backplane

  •  4x 5Gbaud SRIO, 2x AIF2 to FPGA

  •  10 GigE XFI to backplane (TCI6638/66AK2H14 only)

DSP1: Texas Instruments TMS320C6678 Keystone DSP SoC

  •  8 x 1.25GHz C66x DSP cores

  • 2 Gbytes x64 DDR3-1333 SDRAM

  • GigE and HyperLink to DSP0

  • 2x 5Gbaud Gen2 PCIe to backplane

FPGA: Xilinx Kintex-7 K325T

  • FFG676 package allows K160T to K41

  • 1 Gbyte x32 DDR3-1600 SDRAM

  • 256 Mbytes x16 FLASH; allows storage of multiple FPGA configuration images

  •  3x MGT, 32x LVDS, UART to backplan

  •  I2C from each DSP for register access

  •  GigE to DSP0