The AMC520 is a ten-channel ADC (Analog to Digital Converter) with two DAC (Digital to Analog Converter) compliant to the AMC.1 and AMC.2 specification. The unit has an on-board, re-configurable FPGA which interfaces directly to the GbE and PCIe bus.  The FPGA has an interface to the QDR-II+ memory (36 and 72-bit wide). This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host. The AMC520 allows for flexible external clocking as well as internal clocking. The AMC520 has a Trig in/out signal that is sourced from the front panel or port 17. Each input/output goes to the Rear Transition Module (RTM) connector that complies with uTCA.4. Each of the ADC/DAC single ended inputs are converted to differential signals.

The FPGA interfaces directly to the AMC per AMC.1 and AMC.2 and also includes direct front panel interfacing via dual SFP+, raw I/O headers, and LEDs. An RS-232 port is available from the FPGA if the customer desires to implement a soft-processor in the FPGA and have a serial console.

Key Features

ØDouble module AMC, compliant to μTCA.4

ØTen channel of ADC with 125MSPS @ 16-bit resolution utilizing AD9268 device

ØDual DAC with 250 MSPS @ 16-bit resolution utilizing MAX5878 device (this is user programmable for lower sampling rate)

ØInternal clock or precision external clock from RTM/backplane/front panel clocks

ØTrig in/out configurable by software (external trigger via front or port 17)

ØBackplane PCIe Dual x4 or x8/Dual GbE

ØXilinx Virtex-6 FPGA in FF1759 package

ØOption for QDR-II+

ØAMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed

ØDual SFP+ (up to 6.6Gbps)

ØJTAG selectable front and backplane

ØAMC.1 and AMC.2 (FPGA programmable)